Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA
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The adder is a fundamental logic block in most digital processing systems, but it is also a significant source of power consumption due to its high switching frequency. This paper presents the application of the Clock Enable (CE) technique to reduce dynamic power in a 32-bit adder implemented on FPGA. Instead of directly gating the clock signal, the input and output registers of the adder are controlled by the CE signal, maintaining their values when the adder is inactive. Experimental results on a Spartan-3E FPGA show that dynamic power is reduced by approximately 58.6%, total power decreases by 36.6%, and junction temperature drops by 2°C compared to the conventional design. This technique is simple, easy to integrate, and provides significant benefits for low-power digital design.
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