HẰNG, Vũ; KHOI HUY DO. Application of Clock Enable Technique in Power Optimization of a 32-Bit Adder on FPGA. RA Journal of Applied Research, [S. l.], v. 11, n. 11, p. 973–977, 2025. DOI: 10.47191/rajar/v11i11.02. Disponível em: https://rajournals.in/index.php/rajar/article/view/1782. Acesso em: 24 oct. 2026.